idt54/74fct821at/bt/ct, 823/825at/bt/ct/dt high-performance cmos bus interface registers military and commercial temperature ranges 6.21 1 integrated device technology, inc. 1 high-performance cmos bus interface registers the idt logo is a registered trademark of integrated device technology, inc. idt54/74fct821at/bt/ct idt54/74fct823at/bt/ct/dt idt54/74fct825at/bt/ct features: common features: low input and output leakage 1 m a (max.) cmos power levels true ttl input and output compatibility ?v oh = 3.3v (typ.) ?v ol = 0.3v (typ.) meets or exceeds jedec standard 18 specifications product available in radiation tolerant and radiation enhanced versions military product compliant to mil-std-883, class b and desc listed (dual marked) available in dip, soic, ssop, qsop, cerpack and lcc packages features for fct821t/fct823t/fct825t: a, b, c and d speed grades high drive outputs (-15ma i oh , 48ma i ol ) power off disable outputs permit ?ive insertion description: the fct82xt series is built using an advanced dual metal cmos technology. the fct82xt series bus interface regis- ters are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. the fct821t are buffered, 10-bit wide versions of the popular fct374t function. the fct823t are 9-bit wide buffered registers with clock enable ( en ) and clear ( clr ) C ideal for parity bus interfacing in high-performance microprogrammed systems. the fct825t are 8-bit buffered registers with all the fct823t controls plus multiple enables ( oe 1, oe 2, oe 3) to allow multi- user control of the interface, e.g., cs , dma and rd/ wr . they are ideal for use as an output port requiring high i ol /i oh . the fct82xt high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. all inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state. military and commercial temperature ranges august 1995 1995 integrated device technology, inc 6.21 dsc-4202/5 functional block diagram d cp q q cl d cp q q cl d 0 d n y 0 y n en clr cp oe 2567 drw 01
idt54/74fct821at/bt/ct, 823/825at/bt/ct/dt high-performance cmos bus interface registers military and commercial temperature ranges 6.21 2 pin configurations fct821 10-bit register 2567 drw 04 2567 drw 03 fct823 9-bit register 2567 drw 02 index d 2 y 2 y 3 y 4 nc y 5 oe d 1 nc v cc y 0 d 8 gnd cp y 9 y 8 lcc top view 32 20 19 1 4 5 6 7 8 18 17 16 15 14 9 10 11 1213 l28-1 d 3 d 4 nc d 5 d 6 d 7 d 0 y 1 y 6 y 7 21 22 23 24 25 26 27 28 d 9 nc index d 2 y 2 y 3 y 4 nc y 5 oe d 1 nc v cc y 0 lcc top view 32 20 19 1 4 5 6 7 8 18 17 16 15 14 9 10 11 1213 l28-1 d 3 d 4 nc d 5 d 6 d 7 d 8 gnd cp en y 8 d 0 y 1 y 6 y 7 21 22 23 24 25 26 27 28 clr nc index d 1 y 1 y 2 y 3 nc y 4 d 0 nc v cc oe 3 lcc top view 32 20 19 1 4 5 6 7 8 18 17 16 15 14 9 10 11 1213 l28-1 d 2 d 3 nc d 4 d 5 d 6 d 7 gnd cp en y 7 oe 2 y 0 y 5 y 6 21 22 23 24 25 26 27 28 clr nc oe 1 oe d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 gnd y 0 y 1 y 2 y 3 y 4 y 6 cp y 5 y 7 v cc 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 p24-1 d24-1 so24-2 so24-7 so24-8 & e24-1 11 12 21 22 23 24 d 8 clr y 8 en dip/soic/ssop/qsop/cerpack top view oe d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 gnd y 0 y 1 y 2 y 3 y 4 y 6 cp y 5 y 7 v cc 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 p24-1 d24-1 so24-2 so24-7 so24-8 & e24-1 11 12 21 22 23 24 d 8 d 9 y 8 y 9 dip/soic/ssop/qsop/cerpack top view fct825 8-bit register oe 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 gnd y 0 y 1 y 2 y 3 y 4 y 6 cp y 5 y 7 v cc 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 p24-1 d24-1 so24-2 so24-8 & e24-1 11 12 21 22 23 24 dip/soic/qsop/cerpack top view oe 2 clr oe 3 en
idt54/74fct821at/bt/ct, 823/825at/bt/ct/dt high-performance cmos bus interface registers military and commercial temperature ranges 6.21 3 function table (1) pin description 2567 tbl 01 absolute maximum ratings (1) capacitance ( t a = +25 c, f = 1.0mhz) symbol rating commercial military unit v term (2) terminal voltage with respect to gnd ?.5 to +7.0 ?.5 to +7.0 v v term (3) terminal voltage with respect to gnd ?.5 to v cc +0.5 ?.5 to v cc +0.5 v t a operating temperature 0 to +70 ?5 to +125 c t bias temperature under bias ?5 to +125 ?5 to +135 c t stg storage temperature ?5 to +125 ?5 to +150 c p t power dissipation 0.5 0.5 w i out dc output current ?0 to +120 ?0 to +120 ma notes: 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed v cc by +0.5v unless otherwise noted. 2. input and v cc terminals only. 3. outputs and i/o terminals only. note: 1. this parameter is measured at characterization but not tested. 2567 lnk 03 2567 lnk 04 symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf inputs internal/ outputs oe oe clr clr en en d i cp q i y i function h h h h l l l h - - l h z z high z h l l l x x x x x x l l z l clear h l h h h h x x x x nc nc z nc hold h h l l h h h h l l l l l h l h - - - - l h l h z z l h load names i/o description d i i the d flip-flop data inputs. clr i when the clear input is low and oe is low, the q i outputs are low. when the clear input is high, data can be entered into the register. cp i clock pulse for the register; enters data into the register on the low-to- high transition. y i o the register 3-state outputs. en i clock enable. when the clock enable is low, data on the d i input is transferred to the q i output on the low-to-high clock transition. when the clock enable is high, the q i outputs do not change state, regardless of the data or clock input transitions. oe i output control. when the oe input is high, the y i outputs are in the high- impedance state. when the oe input is low, the true register data is present at the y i outputs. note: 2567 tbl 02 1. h = high l = low x = dont care nc = no change - = low-to-high transition z = high impedance
idt54/74fct821at/bt/ct, 823/825at/bt/ct/dt high-performance cmos bus interface registers military and commercial temperature ranges 6.21 4 dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = 0 c to +70 c, v cc = 5.0v 5%; military: t a = C55 c to +125 c, v cc = 5.0v 10% symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2.0 v v il input low level guaranteed logic low level 0.8 v i i h input high current (4) v cc = max. v i = 2.7v 1 m a i i l input low current (4) v i = 0.5v 1 i ozh high impedance output current v cc = max. v o = 2.7v 1 m a i ozl (3-state output pins) (4) v o = 0.5v 1 i i input high current (4) v cc = max., v i = v cc (max.) 1 m a v ik clamp diode voltage v cc = min., i in = C18ma C0.7 C1.2 v v h input hysteresis 200 mv i cc quiescent power supply current v cc = max., v in = gnd or v cc 0.01 1 ma 2567 lnk 05 output drive characteristics for fct821/823/825t symbol parameter test conditions (1) min. typ. (2) max. unit v oh output high voltage v cc = min. v in = v ih or v il i oh = C6ma mil. i oh = C8ma com'l. 2.4 3.3 v i oh = C12ma mil. i oh = C15ma com'l. 2.0 3.0 v v ol output low voltage v cc = min. v in = v ih or v il i ol = 32ma mil. i ol = 48ma com'l. 0.3 0.5 v i os short circuit current v cc = max., v o = gnd (3) C60 C120 C225 ma i off input/output power off leakage (5) v cc = 0v, v in or v o 4.5v 1 m a 2567 lnk 06 notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25 c ambient. 3. not more than one output should be shorted at one time. duration of the short circuit test should not exceed one second. 4. the test limit for this parameter is 5 m a at t a = C55 c. 5. this parameter is guaranteed but not tested.
idt54/74fct821at/bt/ct, 823/825at/bt/ct/dt high-performance cmos bus interface registers military and commercial temperature ranges 6.21 5 power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply current ttl inputs high v cc = max. v in = 3.4v (3) 0.5 2.0 ma i ccd dynamic power supply current (4) v cc = max. outputs open oe = en = gnd one input toggling 50% duty cycle v in = v cc v in = gnd 0.15 0.25 ma/ mhz i c total power supply current (6) v cc = max. outputs open f cp = 10mhz 50% duty cycle v in = v cc v in = gnd 1.5 3.5 ma oe = en = gnd one bit toggling at fi = 5mhz 50% duty cycle v in = 3.4v v in = gnd 2.0 5.5 v cc = max. outputs open f cp = 10mhz 50% duty cycle v in = v cc v in = gnd 3.8 7.3 (5) oe = en = gnd eight bits toggling at fi = 2.5mhz 50% duty cycle v in = 3.4v v in = gnd 6.0 16.3 (5) 2567 tbl 07 notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp/ 2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz.
idt54/74fct821at/bt/ct, 823/825at/bt/ct/dt high-performance cmos bus interface registers military and commercial temperature ranges 6.21 6 switching characteristics over operating range fct821/823/825at fct821/823/825bt com'l. mil. com'l. mil. symbol parameter condition (1) min . (2) max. min . (2) max. min . (2) max. min . (2) max. unit t plh t phl propagation delay cp to y i ( oe = low) c l = 50pf r l = 500 w 1.5 10.0 1.5 11.5 1.5 7.5 1.5 8.5 ns c l = 300pf (4) r l = 500 w 1.5 20.0 1.5 20.0 1.5 15.0 1.5 16.0 t su set-up time high or low d i to cp c l = 50pf r l = 500 w 4.0 4.0 3.0 3.0 ns t h hold time high or low d i to cp 2.0 2.0 1.5 1.5 ns t su set-up time high or low en to cp 4.0 4.0 3.0 3.0 ns t h hold time high or low en to cp 2.0 2.0 0 0 ns t phl propagation delay, clr to y i 1.5 14.0 1.5 15.0 1.5 9.0 1.5 9.5 ns t rem recovery time clr to cp 6.0 7.0 6.0 6.0 ns t w clock pulse width high or low 7.0 7.0 6.0 6.0 ns t w clr pulse width low 6.0 7.0 6.0 6.0 ns t pzh t pzl output enable time oe to y i c l = 50pf r l = 500 w 1.5 12.0 1.5 13.0 1.5 8.0 1.5 9.0 ns c l = 300pf (4) r l = 500 w 1.5 23.0 1.5 25.0 1.5 15.0 1.5 16.0 t phz t plz output disable time oe to y i c l = 5pf (4) r l = 500 w 1.5 7.0 1.5 8.0 1.5 6.5 1.5 7.0 ns c l = 50pf r l = 500 w 1.5 8.0 1.5 9.0 1.5 7.5 1.5 8.0 notes: 2567 tbl 08 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not tested. 4. this condition is guaranteed but not tested.
idt54/74fct821at/bt/ct, 823/825at/bt/ct/dt high-performance cmos bus interface registers military and commercial temperature ranges 6.21 7 switching characteristics over operating range fct821/823/825ct fct823dt com'l. mil. com'l. symbol parameter condition (1) min . (2) max. min . (2) max. min . (2) max. unit t plh t phl propagation delay cp to y i ( oe = low) c l = 50pf r l = 500 w 1.5 6.0 1.5 7.0 1.5 5.0 ns c l = 300pf (4) r l = 500 w 1.5 12.5 1.5 13.5 1.5 8.5 t su set-up time high or low d i to cp c l = 50pf r l = 500 w 3.0 3.0 2.0 ns t h hold time high or low d i to cp 1.5 1.5 1.0 ns t su set-up time high or low en to cp 3.0 3.0 3.0 ns t h hold time high or low en to cp 00 0 ns t phl propagation delay, clr to y i 1.5 8.0 1.5 8.5 1.5 5.0 ns t rem recovery time clr to cp 6.0 6.0 3.0 ns t w clock pulse width high or low (3) 6.0 6.0 3.0 ns t w clr pulse width low (3) 6.0 6.0 3.0 ns t pzh t pzl output enable time oe to y i c l = 50pf r l = 500 w 1.5 7.0 1.5 8.0 1.5 4.8 ns c l = 300pf (4) r l = 500 w 1.5 12.5 1.5 13.5 1.5 9.0 t phz t plz output disable time oe to y i c l = 5pf (4) r l = 500 w 1.5 6.0 1.5 6.0 1.5 4.0 ns c l = 50pf r l = 500 w 1.5 6.5 1.5 6.5 1.5 4.0 notes: 2567 tbl 09 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not tested. 4. this condition is guaranteed but not tested.
idt54/74fct821at/bt/ct, 823/825at/bt/ct/dt high-performance cmos bus interface registers military and commercial temperature ranges 6.21 8 pulse width switch position enable and disable times propagation delay set-up, hold and release times test circuits and waveforms test circuits for all outputs pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. notes: 1. diagram shown for input control enable-low and input control disable- high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns test switch disable low enable low closed all other tests open open drain definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. 2567 drw 05 2567 drw 06 2567 drw 07 2567 drw 08 2567 drw 09 2567 lnk 10
idt54/74fct821at/bt/ct, 823/825at/bt/ct/dt high-performance cmos bus interface registers military and commercial temperature ranges 6.21 9 ordering information xx temp. range xxxx device type x package x process blank b p d e l so py q 821at 823at 825at 821bt 823bt 825bt 821ct 823ct 825ct 823dt commercial mil-std-883, class b plastic dip cerdip cerpack leadless chip carrier small outline ic shrink small outline package quarter-size small outline package 10-bit non-inverting register 9-bit non-inverting register 8-bit non-inverting register 54 74 C55 c to +125 c 0 c to +70 c idt 2567 drw 10
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